Queue buffer memory control system

G - Physics – 06 – F

Patent

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354/241

G06F 13/18 (2006.01) G06F 5/06 (2006.01) G06F 5/16 (2006.01)

Patent

CA 2002537

QUEUE BUFFER MEMORY CONTROL SYSTEM ABSTRACT OF THE DISCLOSURE In a queue buffer memory control system for managing a busy state of data at a queue buffer memory provided between a main storage unit and an external storage unit. The queue buffer memory control system includes: a control unit for receiving a request signal from a central processing unit, selecting the priority order of the request signal and decoding a destination command included in the request signal to determine whether or not the request signal indicates an access to the queue buffer memory; an output data detection unit operatively connected to the queue buffer memory for detecting the data quantity output from the queue buffer memory and outputting a detection signal at every detection of the data; an input data detection unit operatively connected to an output side of the control unit for detecting existence of data to be transferred to the queue buffer memory based on the destination command of the request signal, and outputting a detection signal when the input data detection unit detects the request signal before the main storage unit receives the request signal; and a data read/write indication unit operatively connected to the input data detection unit and the output data detection unit for detecting the data quantity to be transferred to the queue buffer memory based on the difference between the detection signals, and generating a stop signal to the control unit for stopping an input of the request signal having the destination command of the data transfer from the main memory unit to the queue buffer memory when the data quantity at the queue buffer memory reaches a predetermined maximum quantity.

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