G - Physics – 11 – C
Patent
G - Physics
11
C
G11C 11/4195 (2006.01) A61K 31/4164 (2006.01) A61K 31/4184 (2006.01) A61K 31/496 (2006.01) A61K 31/5377 (2006.01) A61K 31/541 (2006.01) G11C 11/408 (2006.01)
Patent
CA 2342472
A row addressing circuit for DRAM memory is disclosed. An additional address or mode bit is used to select between a long page and a short page mode access in each memory block within a memory array. The operation is done on the fly, allowing the user to dynamically choose between the addressing modes. Each memory block is divided into two sub-blocks, each having its own set of bitlines, associated bitline sense amplifiers and y- decoders. In the short page mode access, only one wordline in the memory block is activated. In the long page mode access, one wordline in each sub-block is activated. Therefore, twice the number of bits can be accessed in the long page mode access over the short page mode access. The addressing circuit also generates the necessary enable signals to ensure that the bitline sense amplifiers and y-decoders of both sub-blocks are enabled during the long page access mode.
Kowalczyk Dariusz
Kurjanowicz Wlodek
Popoff Greg
Wiatrowski Jacek
Atmos Corporation
Borden Ladner Gervais Llp
Kowalczyk Dariusz
Kurjanowicz Wlodek
Popoff Greg
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