Random access memory dual word line recovery circuitry

Details Random access memory dual word line recovery circuitry Random access memory dual word line recovery circuitry

H - Electricity

03

K

328/81

H03K 5/00 (2006.01) G11C 8/08 (2006.01) G11C 11/413 (2006.01)

Patent

CA 1177910

ABSTRACT A discharge circuit for rapidly discharging the word lines of random access memories to thereby prevent erroneous reading from or writing into the memory during periods when the word lines are in a mid-state transition between selected and deselected voltage levels. Each discharge circuit associated with the memory word lines includes a transistor that is conductive only when a full select voltage level is applied to the word line and which controls conduction of a second multi-collector transistor coupled between top and bottom lines of a word line pair and a current source to discharge the word line pair during the mid-state transition period and to thus increase the speed capabilities of the memory.

407086

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