Range count and main memory address accounting system

Details Range count and main memory address accounting system Range count and main memory address accounting system

G - Physics

06

F

354/237

G06F 9/30 (2006.01) G06F 5/10 (2006.01) G06F 13/12 (2006.01) G06F 13/28 (2006.01)

Patent

CA 1115424

RANGE COUNT AND MAIN MEMORY ADDRESS ACCOUNTING SYSTEM ABSTRACT OF THE DISCLOSURE In a peripheral controller of a data processing system having a plurality of system units electrically coupled to a common communication bus for asynchronous intercommunication, an array of counters responsive to both hardware and firmware are connected in a manner to form a serial control data path. Prior to a data transfer, a serial data stream including an offset range count, a range count and a main memory address is shifted through the counters under firmware control. During a data transfer, the firmware enables the hardware control to increment the memory address and decrement the range count to accommodate the higher data transfer rates characteristic of hardware control.

304098

Affiliated with

Also associated with

Rating

Range count and main memory address accounting system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Range count and main memory address accounting system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Range count and main memory address accounting system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-385690