G - Physics – 06 – G
Patent
G - Physics
06
G
354/150
G06G 7/20 (2006.01) G06J 1/00 (2006.01)
Patent
CA 1182566
-12- RATE MULTIPLIER SQUARE ROOT EXTRACTOR WITH INCREASED ACCURACY FOR TRANSMITTER APPLICATIONS ABSTRACT OF THE DISCLOSURE Circuitry for extracting the square root of an incoming voltage signal is disclosed. The circuit (10) utilizes a four-bit up/down counter (14) to control the output duty cycle of a pair of four-bit rate multipliers (16, 18) connected in a cascaded configuration. The output of the second rate multiplier (18), which is related to the square of the up/down counter value, is used to control the mode of the counter (14) so as to track the incoming voltage signal. Inasmuch as the square of the up/down counter value is tracking the incoming voltage sig- nal, the output duty cycle of the first rate multiplier (16) in the cas- caded pair is the square root of the incoming voltage signal which is subsequently converted into analog form. The circuit also utilizes a "dithering" technique so that the resulting square root output signal has greater than four-bit accuracy.
431558
Keyes Marion A. IV
Thompson William L.
Babcock & Wilcox Company The
Ridout & Maybee Llp
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