H - Electricity – 01 – L
Patent
H - Electricity
01
L
204/96.05
H01L 21/308 (2006.01) H01L 21/28 (2006.01) H01L 21/3213 (2006.01)
Patent
CA 1202597
-1- Abstract: An advantageous low-resistivity gate level metallization for VLSI MOS devices comprises TaSi2 on polysilicon. A two-layer tantalum-silicon composite initially overlies a relatively thin gate oxide film. In accordance with this invention, the two-layer composite is anisotropically patterned in a two-step reactive ion etch- ing process. Patterning is carried out before the layers are sintered to form TaSi2. In the preferred embodiment, CC13F is utilized to etch the composite layer and some of the underlying polysilicon layer. Thereafter, utilizing C12, the remaining polysilicon is etched in a step characterized by high selectivity with respect to the underlying gate oxide film.
401014
Deslauriers Jean S.
Levinstein Hyman J.
Kirby Eades Gale Baker
Western Electric Company Incorporated
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