Read only memory

Details Read only memory Read only memory

G - Physics

11

C

352/82.3, 352/41

G11C 11/44 (2006.01) G11C 5/02 (2006.01) G11C 17/12 (2006.01)

Patent

CA 1078064

READ ONLY MEMORY Abstract of the Disclosure A read only memory is organized as a matrix of field effect transistors wherein logic levels are determined by the presence or absence of a gate which permits transis- tor action. The memory is addressed using a gate decode tree which selects the gates of a column of matrix devices and a source decode tree which selects the source lines of a row of matrix devices. Sensing of the logic level at a selected location is accomplished by a change of state output sense circuit which dymanically senses and provides a static output using a polarity hold circuit. Clamped, boot-strapped inverter circuits are provided in both input and output circuitry to maintain voltage, at selected inter- nal nodes at a voltage intermediate predetermined minimum and maximum values.

254960

Affiliated with

Also associated with

Rating

Read only memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Read only memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Read only memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-756345