Real time clock recovery circuit

Details Real time clock recovery circuit Real time clock recovery circuit

H - Electricity

04

L

340/165

H04L 7/00 (2006.01) H04L 7/02 (2006.01)

Patent

CA 1161518

REAL TIME CLOCK RECOVERY CIRCUIT Abstract of the Disclosure This invention relates to a real time clock recovery circuit. The clock recovery circuit requires three inputs, a bit serial data received input (BSD), a quarter bit delayed (QBT) and a three quarter bit de- layed (TQBT) signal. The three inputs are derived from a single raw input that becomes the received input (BSD) signal. QBT and TQBT are delay line versions of the BSD signal. The three inputs (BSD, QBT and TQBT, and the complement of these signals) are ANDed together to detect low frequencies. The generated signal indicative of the low frequency, QBT and TQBT generate a recovered clock by state sequencing of an R-S latch. The type of bit serial data stream which may be inputted to the circuit of the present invention is double frequency encoded data streams, including Manchester or diphase encoded.

391588

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