H - Electricity – 03 – K
Patent
H - Electricity
03
K
354/105, 328/114
H03K 19/14 (2006.01) H04B 10/152 (2006.01) H04L 25/49 (2006.01)
Patent
CA 1161503
SPECIFICATIONS OF Edwin M. Petryk Jr. A RECEIVER APPARATUS FOR CONVERTING OPTICALLY ENCODED BINARY DATA TO ELECTRICAL SIGNALS ABSTRACT OF THE DISCLOSURE There is disclosed herein an apparatus for receiving optically encoded binary data transmitted over an optical fiber from an optical transmitter device coupled to another data processing system. The receiver apparatus is used to convert the light signal carrying the subject data into TTL level digital logic signals. The receiver apparatus is comprised of circuity for converting the optically encoded data into electrical signals in serial format, and circuitry for converting these electrical signals into TTL level digital signals in parallel format for use by a user device. The primary advantage of the apparatus disclosed herein is the ability to substitute a single optical fiber for a plurality of parallel copper wires for carrying data between one data processing device and another with little or no loss in speed due to the larger band- width of optical fibers. Another significant advantage is the ability to couple data processing systems directly over much larger distances than possible with average cost parallel copper wire electrical cables. Higher noise immunity and communications security is also enjoyed. In the preferred embodiment, the receiver apparatus comprises a photodiode for converting the light signal into an electrical signal followed by an amplifier for changing the electrical signal to TTL digital logic levels. A clock generator and header detector recover a clock signal and detect the receipt of a header signal indicating transmission of a serial format data packet has commenced. A serial in and parallel out shift register/data latch storage buffer combination utilizes a signal derived from the recovered clock signal to shift the incoming data bits into the shift register and latch them into the data latch output buffers in parallel format when a counter signals that an entire data packet has been received. 5202819
356821
Honeywell Information Systems Inc.
Smart & Biggar
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