Receiver equipped with a trellis viterbi decoder

Details Receiver equipped with a trellis viterbi decoder Receiver equipped with a trellis viterbi decoder

H - Electricity

03

M

H03M 13/41 (2006.01) G01S 19/37 (2010.01) H04B 1/16 (2006.01) H04L 1/22 (2006.01)

Patent

CA 2707198

The invention relates to a receiver of a digital signal equipped with an N-state weighted-decision trellis Viterbi decoder, the signal received comprising a series of symbols. It includes a programmable logic circuit which comprises: - a source memory A (10) and a destination memory B (20) each comprising N rows and M+L columns respectively allocated to M fixed fields for describing the trellis, and to L variable fields, - an operator (30) able to calculate the variable fields of a memory as a function of the fixed fields of the said memory, of the symbols received and of the variable fields of the other memory and able to reverse the role of the source memory (10) and destination memory (20).

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