Receiver for pulse code multiplexed signals

Details Receiver for pulse code multiplexed signals Receiver for pulse code multiplexed signals

H - Electricity

04

J

363/13

H04J 3/06 (2006.01)

Patent

CA 1136780

A B S T R A C T Simple and reliable decoding of T-1 type pulse code information is achieved by combining a fast-acting recirculating frame recovery circuit with a simplified signal output register. The frame recovery circuit uses a recir- culating 386-bit control word in which all positions which cannot be the main-frame bit position are continuously recorded by the continuous comparison of pairs of incoming data bits spaced 386 bits apart. Following a sufficient number of iterations of the control word to statistically identify all 385 non-main-frame-bit positions with a nigh degree of probability, the remaining unidentified position is read out as the main-frame bit position, and is used to reset the frame clock generator. The signalling pulses recovered from the correctly framed data train are distributed to the proper channel relays by a simplified output circuit which loads the signalling bits into a buffer register at a slow rate dictated by the data train parameters, then unloads the buffer register into the output latches at a rate suf- ficiently fast to make it impossible for the channel relays to spuriously respond to momentary invalid signals occurring during the unloading process.

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