Receiver for synchronous signals with double phase-locked loop

Details Receiver for synchronous signals with double phase-locked loop Receiver for synchronous signals with double phase-locked loop

H - Electricity

03

K

325/80

H03K 9/02 (2006.01) H04L 7/02 (2006.01) H04L 7/027 (2006.01) H04L 27/14 (2006.01) H04L 27/152 (2006.01)

Patent

CA 1066782

ABSTRACT In a receiver for synchronous data signals of the type in which a frequency component is produced at the symbol frequency by means of a non-linear signal processing circuit to derive therefrom a reference sig- nal by means of a phase-locked loop, the phase comparison circuit is constructed from two phase detectors, a reference circuit and an output circuit to prevent large phase fluctuations of the reference signal when long series of identical symbols are produced in the data signal.

266007

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