Reconfigurable memory system

Details Reconfigurable memory system Reconfigurable memory system

G - Physics

06

F

354/239, 352/41,

G06F 12/06 (2006.01) G06F 12/04 (2006.01) G06F 12/08 (2006.01)

Patent

CA 1226673

ABSTRACT Apparatus and method for reconfiguring a memory in a data processing system to increase the rate of information transfer between system memory and processor. The system memory is comprised of a plurality of memory banks, each bank being one or more words in width and having a separate data output path. In a first configuration a memory controller addresses the memory banks as a sequential memory to read from one address location at a time and the output data paths of the memory banks are configured into a single, one bank wide data path to the system processor. If each bank is one word wide and N words deep and there are M memory banks, the memory appears as a sequential, one word wide by MxN words deep memory from which one word may be read at a time. In a second configuration, the memory is reconfigured by the addition of an address translator means and a bus reconfigur- ation means. The address translator means provides addresses addressing M banks in parallel, so that M locations are read in each read operation. The bus reconfiguration means reconfigures the bank output busses in parallel, that is, into M parallel busses, and provides a selection means, responsive to the addres- sing means, for providing the information appearing on a selected bank output bus as the memory output to the system processor. The memory is thereby reconfigured to be a parallel, M words wide by N words deep memory wherein M words may be read from the memory at a time. In both the sequential and parallel configurations, the data path to the system processor, that is, the combined single width path of the sequential configuration and the selec- tion means output of the parallel configuration, comprise a direct data path from the memory to the processor. In a further embodiment, a cache path is provided, connected in parallel with the direct data path, that is, from the parallel bank outputs to selection means output, or storing information in advance of information presently being processed.

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