Reduced instruction set computing apparatus and methods

Details Reduced instruction set computing apparatus and methods Reduced instruction set computing apparatus and methods

G - Physics

06

F

354/193

G06F 9/30 (2006.01) G06F 9/318 (2006.01) G06F 9/455 (2006.01) G06F 15/78 (2006.01)

Patent

CA 1278382

Abstract Reduced Instruction Set Computing Apparatus and Methods A reduced instruction set computer (RISC) with a Harvard architecture is disclosed. The RISC may be designed to be used simply as a RISC or may be designed to be used to emulate a complex instruction set computer (CISC). Or, it may be designed for use as either. A CISC design methodology is disclosed whereby a RISC is designed and fabricated and whereby RISC emulation code is written concurrently with design and fabrication and also subsequent to fabrication.

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