Reduced power tristate circuit

Details Reduced power tristate circuit Reduced power tristate circuit

H - Electricity

03

K

328/130

H03K 19/094 (2006.01) H03K 5/02 (2006.01) H03K 19/00 (2006.01) H03K 19/20 (2006.01)

Patent

CA 1157110

PF 77E152 Abstract A tristate driver circuit is provided having a logic input signal, to produce a logic 1 output level or a logic 0 output level, and a float input signal, to produce float state operation. The circuit comprises a first logic gate powered by a first buffer switch, a second logic gate powered by a second buffer switch, an output driver having a first signal driver input from the output of the first gate and a second signal driver input from the output of the second gate; the first and second buffer switches dissipating the greatest circuit power during the circuit float state operation, and means, coupled to the first and second buffer switches and to the source of float signal input signal, for interrupting power to the first and second buffer switches responsive to onset of the float state operation.

371572

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