H - Electricity – 04 – J
Patent
H - Electricity
04
J
H04J 3/07 (2006.01)
Patent
CA 2349344
Circuits and methods are described which reduce waiting time jitter at a synchronizer/multiplexer by using a "sub-bit" comparison of a clock associated with an unsynchronized data stream and a clock associated with a synchronized data stream to generate a threshold level for use in determining when to stuff bits into the synchronized data stream. The term "sub-bit" means that the phase difference, as measured by, for example, the location of pointers associated with the two clocks, is precise to a fraction of a bit.
La présente invention concerne des circuits et des procédés permettant de réduire la gigue de justification d'un synchroniseur/multiplexeur par une comparaison "sub-bit" d'un signal d'horloge associé à un train de données non synchronisé et d'un signal d'horloge associé à un train de données synchronisé, afin de générer un niveau seuil qui permet de déterminer à quel moment envoyer des bits de complément dans le train de données synchronisé. L'expression <= sub-bit >= signifie que le déphasage, mesuré notamment sur la base de la position des pointeurs associés aux deux signaux d'horloge, est de l'ordre d'une fraction de bit.
Adc Telecommunications Inc.
Gowling Lafleur Henderson Llp
LandOfFree
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