Redundancy scheme for an mos memory

Details Redundancy scheme for an mos memory Redundancy scheme for an mos memory

G - Physics

11

C

352/40

G11C 8/00 (2006.01) G11C 29/00 (2006.01)

Patent

CA 1176371

REDUNDANCY SCHEME FOR AN MOS MEMORY ABSTRACT OF THE DISCLOSURE A redundancy scheme is described for use with an MOS memory having a main array of memory cells, and a plurality of spare memory cells. Typically, each memory cell is tested for operability by a conventional probe test. When a defective memory cell is found, an on-chip address controller responds to the probe test finding a defective cell-by permanently storing and rendering continuously available a fully asynchronous electrical indication of the address of the defective cell. The address controller compares its stored data with memory cell information received during normal memory operation, and generates a control signal indicative of the receipt of an address which corresponds to a defective cell. A spare cell selector responds to the control signal by electrically accessing a spare memory cell and by pro- hibiting access of the defective memory cell.

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