Redundancy system for non-volatile memory

Details Redundancy system for non-volatile memory Redundancy system for non-volatile memory

G - Physics

11

C

G11C 29/00 (2006.01) G11C 17/18 (2006.01)

Patent

CA 2708593

A redundancy scheme for Non-Volatile Memories (NVM) is described. This redundancy scheme provides means for using defective cells in non-volatile memories to increase yield. The algorithm is based on inverting the program data for data being programmed to a cell grouping when a defective cell is detected in the cell grouping. Defective cells are biased to either "1" or "0" logic states, which are effectively preset to store its biased logic state. A data bit to be stored in a defective cell having a logic state that is complementary to the biased logic state of the cell results in the program data being inverted and programmed. An inversion status bit is programmed to indicate the inverted status of the programmed data. During read out, the inversion status bit causes the stored data to be re--inverted into its original program data states

Affiliated with

Also associated with

Rating

Redundancy system for non-volatile memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Redundancy system for non-volatile memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Redundancy system for non-volatile memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1381589