Redundant clock and frame pulse synchronization system

Details Redundant clock and frame pulse synchronization system Redundant clock and frame pulse synchronization system

H - Electricity

04

J

363/13

H04J 3/06 (2006.01) H04L 7/033 (2006.01)

Patent

CA 1302594

ABSTRACT Apparatus and method for synchronizing data signals transferred between independent processors within a communication system. The data signals are received from a first one of the processors synchronized to a first clock signal, and are then latched into a dual port RAM synchronized to a second clock signal. according to a preferred embodiment, the data signals are PCM signals which are loaded into the dual port RAM in accordance with address signals corresponding to PCM channel numbers associated with the first processor, and the data signals are read from the dual port RAM in accordance with address signals corresponding to PCM channel numbers associated with the second processor.

571908

Affiliated with

Also associated with

Rating

Redundant clock and frame pulse synchronization system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Redundant clock and frame pulse synchronization system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Redundant clock and frame pulse synchronization system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1211837