G - Physics – 11 – C
Patent
G - Physics
11
C
G11C 11/4197 (2006.01) G11C 11/409 (2006.01) G11C 11/4099 (2006.01) H01L 27/108 (2006.01)
Patent
CA 2342508
A DRAM having integration capacitors coupled to dummy memory cells of a folded bitline arrangement is disclosed. The dummy memory cells are identical to normal memory cells, and store a midpoint voltage via equalization between the dummy memory cell having a logic "1" voltage potential and the dummy memory cell having a logic "0" voltage potential. The integration capacitor supplies additional charge to both dummy cell storage capacitors during the equalization operation to compensate for bitline voltage differences during various access cycles.
Atmos Corporation
Borden Ladner Gervais Llp
Kurjanowicz Wlodek
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