Reference cells with integration capacitor

Details Reference cells with integration capacitor Reference cells with integration capacitor

G - Physics

11

C

G11C 11/4197 (2006.01) G11C 11/24 (2006.01) G11C 11/4099 (2006.01) H01L 27/108 (2006.01)

Patent

CA 2379896

A DRAM having integration capacitors coupled to dummy memory cells of a folded bitline arrangement is disclosed. The dummy memory cells are identical to normal memory cells, and store a midpoint voltage via equalisation between the dummy memory cell having a logic "1" voltage potential and the dummy memory cell having a logic "0" voltage potential. The integration capacitor shares charge with both dummy cell storage capacitors during an equalisation operation to compensate for bitline voltage differences during various access cycle.

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