Refresh control arrangement for dynamic random access memory...

G - Physics – 11 – C

Patent

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G11C 7/00 (2006.01) G11C 8/18 (2006.01) G11C 11/406 (2006.01)

Patent

CA 2103594

2103594 9214251 PCTABS00014 A memory controller (14) for controlling a memory (11) including at least one memory bank (15). The memory controller (14) comprises a memory access control circuit (20) that receives memory access request over a bus and for performing a memory access operation in connection with a storage location in response thereto, a memory refresh control circuit (23) includes a yellow and a red refresh control circuit (91). The yellow refresh control circuit (90) initiates a refresh operation in operation with a memory bank other than the bank which the memory access control circuit is performing a memory access operation. The red refresh control circuit (91), on the other hand, initiates a refresh operation in connection with at least one memory bank and concurrently disables said memory access control circuit from performing a memory access operation.

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