Register selection mechanism and organization of an...

G - Physics – 11 – C

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354/237

G11C 5/02 (2006.01) G06F 9/38 (2006.01) G06F 12/04 (2006.01) G11C 7/00 (2006.01)

Patent

CA 1233270

ABSTRACT A register selection mechanism is disclosed for an instruction prefetch buffer which allows instructions having different lengths to be accessed on the instruction boundaries. The instruction prefetch buffer comprises a one-port-write, two-port-read array (10). Address generation and control logic (16) is responsive to a read pointer (15) for controlling access to odd and even addresses in the array. Additional logic may be provided to provide an indication that the instruction prefetch buffer is empty.

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