Regulated mos substrate bias voltage generator for a static...

Details Regulated mos substrate bias voltage generator for a static... Regulated mos substrate bias voltage generator for a static...

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H03L 1/00 (2006.01) G05F 3/20 (2006.01) G11C 5/14 (2006.01) G11C 11/413 (2006.01) H02M 3/07 (2006.01) H03K 3/353 (2006.01)

Patent

CA 1183951

ABSTRACT A regulated substrate bias voltage generating system for maintaining a minimum data retaining current through an associated MOS memory. The negative sub- strate bias voltage is generated by a charge pump operating under the control of a two-phased output oscillator, the operation of which is enabled and disabled by the output signals from a MOS memory over- current sensor, a MOS memory under-current sensor, and a bias voltage level sensor.

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