Remote data link address sequencer and a memory arrangement...

Details Remote data link address sequencer and a memory arrangement... Remote data link address sequencer and a memory arrangement...

H - Electricity

04

J

354/233, 344/29

H04J 1/10 (2006.01) H04J 3/08 (2006.01) H04Q 11/06 (2006.01)

Patent

CA 1220285

A REMOTE DATA LINK ADDRESS SEQUENCER AND MEMORY ARRANGEMENT FOR ACCESSING AND STORING DIGITAL DATA ABSTRACT OF TEE DISCLOSURE An address sequencer and memory arrangement is shown for transferring data in the form of message bytes to and from a plurality of digital data links. The address sequencer and memory arrangement includes a memory circuit having a plurality of memory location areas associated with each of the plurality of digital data links. A counter circuit connected to the memory circuit is loaded with a preset count by a link pro- cessor complex. The counter increments and outputs to the memory circuit addresses which sequentially access each of the memory location areas, transferring each message byte to a data link output buffer for transmission over a respective one of the plurality of digital data links. Alternatively, the counter addresses sequentially each memory location area transferring a message byte to each memory location area from each of the plurality of digital data links via a data link input buffer.

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