Resynchronizing circuit for time division multiplex system

Details Resynchronizing circuit for time division multiplex system Resynchronizing circuit for time division multiplex system

H - Electricity

04

J

363/17

H04J 3/06 (2006.01) H04J 3/07 (2006.01)

Patent

CA 1147876

Abstract of Disclosure The invention relates to input and output circuits for multiplexing equipment, especially the kind used in telephone systems where nominally identical clocking signals have natural deviations of timing (called "plesiochronous" signals). The invention uses the "justification" principle to ensure the clock synchronization of plesiochronous numerical signals. A buffer memory, with independent writing and reading capabilities, is formed of two first in-first out or "FiFo" memories connected in series. The request signal for a "justification" is made when a connection is completed between an IR (Input-Ready) output of the second FiFo memory and an input SO (Shift-Out) of the first FiFo memory, if there is an undesirable phase shift between the input and output clocking system. A reading clock oscillator has a frequency which is governed by a governing signal, which depends, at least in part, upon the electrical state existing in the series connection between the IR output of the second FiFo memory and the input SO of the first FiFo memory. The receiving and demultiplexing system uses a similar buffer memory to extract any "justification" signals which were added on transmission. A phase-locked loop including a quartz-controlled oscillator controls the output clocking of the demultiplexer.

345972

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