Ring core memory arrangement

Details Ring core memory arrangement Ring core memory arrangement

G - Physics

11

C

352/40.5

G11C 5/04 (2006.01) G11C 17/02 (2006.01) G11C 29/00 (2006.01)

Patent

CA 1043459

TITLE RING CORE MEMORY ARRANGEMENT ABSTRACT OF THE DISCLOSURE Word wires are threaded through some cores of a module for bit "1" and around others for bit "0". A current ramp pulse from a selected memory driver through a word wire to a selected memory switch produces an output in sense windings on the cores with bit "1". The current ramp is pro- duced with two generators, one on the driver side and one on the switch side. The drivers and switches are simple current gates with a pulse transformer and a transistor, which along with other current gates are selected from an address register to steer the current ramp. There are up to 8 modules with sense windings in multiple via a twisted pair to a differential sense amplifier. Each sense winding has a decoupling diode to the twisted pair, and a resistor across the winding to clear it down. There may be up to 3 or 4 units each having 8 modules, each unit having its own select circuits and sense amplifiers; with common timing circuits and common output receivers with a twisted pair balanced input multiple from the sense amplifiers, to supply the output to common latches. The system is dupli- cated except for the core modules, but each core has two sense windings. Fault detection includes a circuit having a common resistor for supplying a bias voltage to all memory switches of a unit. Two comparators check the voltage across this resistor, the first to give an output if any switch is turned on, and the second to give an output if more than one switch is turned on. These outputs are sampled and interpreted by the central processor. Various checks may be made for shorts or opens in the memory switches, drivers, diodes, etc. by programming techniques and information in special word wires.

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