Robust delay fault built-in self-testing method and apparatus

Details Robust delay fault built-in self-testing method and apparatus Robust delay fault built-in self-testing method and apparatus

G - Physics

01

R

G01R 31/3187 (2006.01) G01R 31/30 (2006.01) G06F 11/267 (2006.01)

Patent

CA 2145403

This invention relates to a method and apparatus for robust delay fault testing of integrated circuits (IC) (22) with built-in self testing. Hazardous nodes (28) of the IC (22) are determined. The topology of the IC (22) can be modified to include cut-point (23) at the hazardous nodes (28) of the circuit (22). Input (24) to the cut-point (23) is diverted to an observation point (30). A first output MISR (25) provides a signature for the outputs (27) of the IC (22). A cut-point multi-input signature register (MISR) (30) The observation point generates a first signature. During testing a hazard-free input pattern is applied to the IC (22) and the generated first and second signatures are compared to known correct signatures.

L'invention concerne un procédé et un appareil de test automatique intégré d'anomalie de retard de circuits intégrés (IC) (22). On détermine les noeuds (28) du circuit intégré présentant des risques. On peut modifier la topologie du circuit intégré (22) de manière à inclure un point de coupure (23) au niveau des noeuds (28) présentant des risques. L'entrée (24) au point de coupure (23) est déviée vers un point d'observation (30). Un premier registre de signature à entrées multiples (MISR) (25) de sortie génère une signature pour des sorties (27) du circuit intégré (22). Un MISR (30) de point de coupure au niveau du point d'observation génère une première signature. Pendant le déroulement du test, une configuration d'entrée sans risques est appliquée au circuit intégré (22) et les première et deuxième signatures générées sont comparées à des signatures correctes connues.

Affiliated with

Also associated with

Rating

Robust delay fault built-in self-testing method and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Robust delay fault built-in self-testing method and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Robust delay fault built-in self-testing method and apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1948712