H - Electricity – 01 – L
Patent
H - Electricity
01
L
H01L 23/60 (2006.01) H01L 21/336 (2006.01)
Patent
CA 2755284
A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are dis-closed. A circuit (200) includes a middle junction control circuit (250) that turns off a top NFET (225) of a stacked NFET electrostatic discharge (ESD) protection circuit (pad 215, ground 220, top NFET 225, bottom NFET 230, top resistor 235, and bottom resistor 240) during an ESD event.
La présente invention se rapporte à un circuit de protection ESD solide, à un procédé et à une structure de conception pour conceptions tolérantes et de sécurité. Un circuit (200) comprend un circuit de commande de jonction intermédiaire (250) qui désactive un NFET supérieur (225) d'un circuit de protection contre les décharges électrostatiques (ESD) d'un NFET empilé (pastille 215, masse 220, NFET supérieur 225, NFET inférieur 230, résistance supérieure 235, et résistance inférieure 240) en cas d'ESD.
Campi John B.
Chang Shunhua T.
Chatty Kiran V.
Gauthier Robert J.
Li Junjun
International Business Machines Corporation
Wang Peter
LandOfFree
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