Rom-based parallel digital arithmetic device

G - Physics – 06 – F

Patent

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354/151

G06F 7/552 (2006.01)

Patent

CA 1162310

Abstract The present invention relates to a digital parallel square-function data processor. The processor has a parallel N-bit word input and a parallel 2N-bit output for providing an output corresponding to the square of the value of an input address applied thereto. The processor is comprised of a square function ROM having an address input which is responsive to the parallel input, and a read-out coupled to the parallel output but for two output lines of the parallel output. A coincidence gate is provided having one input which is responsive to an end bit of a combination of parts of the parallel input and further having a second input which is responsive to a preselectively biased balance of the combination of parts of the parallel input. A unit is provided for doubling the digital value of the output of the gate. An adder is provided for additively combining the doubled output with the output of the ROM.

421887

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