Rom protection scheme

G - Physics – 06 – F

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354/243, 354/67

G06F 12/14 (2006.01) G06F 21/00 (2006.01) H03M 7/14 (2006.01) G06F 1/00 (2006.01)

Patent

CA 1234920

ROM PROTECTION SCHEME Jerry R. Bauer ABSTRACT A means is provided for encoding and decoding data transmitted by a parallel data bus line (8). An encoding Exclusive-OR gate (23-l through 23-N) is provided for each data transmission lead. One input lead of each encoding Exclusive-OR gate (23-l through 23-N) is con- nected to the corresponding incoming data transmission lead in order to receive data to be transmitted on acces- sible data lines (8-l through 8-N). The other input lead of each encoding Exclusive-OR gate (23-l through 23-N) is connected via a code matrix (22) to a source of a random M-bit binary number (21). The output signal provided by each Exclusive-OR gate is the encoded data bit which is applied to one of the accessible data lines (8-l through 8-N). The encoded data is decoded by a circuit similar to the encoding circuit. In the decoding circuit a decoding Exclusive-OR gate (33-l through 33-N) is provided for each data transmission lead. One input lead of each decoding Exclusive-OR gate (33-l through 33-N) is con- nected to an incoming encoded data transmission lead (8-l through 8-N). The other input lead to the decoding Exclusive-OR gate (33-l through 33-N) is connected via a code matrix (32) which is similar to the code matrix provided in the encoding circuit (22), to a source of a random M-bit binary number (31), where the M-bit binary number provided is the same M-bit binary number provided in the encoding circuit (21). The output leads of the decoding Exclusive-OR gates (33-l through 33-N) are the transmission lines which carry the decoded data (9-l through 9-N). The data on bus lines running between integrated circuits, and which therefore may be intercepted through the use of logic probes, is in encoded form, thereby substantially increasing the effort required to illicitly determine the data stored in firmware.

481906

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