G - Physics – 11 – C
Patent
G - Physics
11
C
354/239, 352/82
G11C 11/40 (2006.01) G06F 12/06 (2006.01) G11C 11/407 (2006.01)
Patent
CA 1138108
ABSTRACT OF THE DISCLOSURE A memory subsystem includes at least one up to a number of memory module boards identical in layout and construction. The board includes a number of memory chips which are positioned at an initial physical row location providing a predetermined number of addressable contiguous memory locations corresponding to a pre- determined increment of memory capacity. The board further includes a register for receiving address sig- nals for accessing the contents of a memory location, rotating chip selection circuits which include a set of switches and an arithmetic unit having first and second sets of input terminals. The first set of input terminals is connected to the register for receiving predetermined ones of the address signals representative of the physical row of chips being addressed and the second set of input terminals are connected to receive signals from the set of switches. The arithmetic unit operates to perform a predetermined arithmetic opera- tion upon the signals applied to the sets of input terminals to generate a set of logical row address signals for enabling the number of chips at the initial row location.
325885
Nibby Chester M.
Panepinto William
Honeywell Information Systems Inc.
Smart & Biggar
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