Round off correction logic for modified booth's algorithm

Details Round off correction logic for modified booth's algorithm Round off correction logic for modified booth's algorithm

G - Physics

06

F

354/182

G06F 11/00 (2006.01) G06F 7/52 (2006.01)

Patent

CA 1119728

ROUND OFF CORRECTION LOGIC FOR MODIFIED BOOTH'S ALGORITHM MULTIPLIER Abstract of the Disclosure A round off correction logic circuit is disclosed for inclusion within a floating point arithmetic binary digital multiplier implementing a modified Booth's algorithm for generating a final product of binary digits. The round off logic circuitry is connected in the mul- tiplier for rounding its final product off to a predeter- mined binary digit without requiring the multiplier to generate any of the less significant binary digits to the right of the predetermined binary digit. Multiplier circuitry otherwise required to generate an unrounded final product prior to round off is eliminated without loss of accuracy in round off.

338112

Affiliated with

Also associated with

Rating

Round off correction logic for modified booth's algorithm does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Round off correction logic for modified booth's algorithm, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Round off correction logic for modified booth's algorithm will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-572544