Routing and forwarding table management for network...

H - Electricity – 04 – L

Patent

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Details

H04L 29/10 (2006.01) H04L 12/56 (2006.01)

Patent

CA 2469874

A computer system having a network processor comprising a core processor and at least one microengine (1-6) in operative communication with the core processor is provided. A table comprised of a plurality of entries with IP addresses associated therewith is built, wherein the entries are organized hierarchically according to an LC-Trie compression algorithm operating on the IP addresses. An Information packet is received within the computer system, wherein the information packet has a destination IP address associated therewith. The table is searched using an LC-Trie search algorithm to find a match between an IP address of an entry in the table and the destination IP address of the information packet. The information packet is transmitted to a forwarding IP address associated with the IP address of the matching entry. An interface is provided to accommodate communication between the core processor and microengine of the network processor.

L'invention concerne un système informatique possédant un processeur de réseau qui comprend un processeur de base et au moins un micromoteur en contact fonctionnel avec le processeur de base. Une table constituée de plusieurs entrées possédant des adresses IP associées est construite, ces entrées étant organisées de façon hiérarchique en fonction d'un algorithme de compression LC-TRIE agissant sur les adresses IP. Un paquet d'informations est reçu dans le système informatique, ce paquet d'informations possédant une adresse IP de destination associée. La table est cherchée au moyen de l'algorithme LC-TRIE en vue de trouver une correspondance entre une adresse IP d'une entrée dans la table et une adresse IP de destination du paquet d'informations. Le paquet d'informations est transmis à une adresse IP de réacheminement associée à l'adresse IP de l'entrée correspondante. L'invention concerne également une interface permettant d'aménager une communication entre le processeur de base et le micromoteur du processeur de réseau.

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