Row driver circuit for semiconductor memory

Details Row driver circuit for semiconductor memory Row driver circuit for semiconductor memory

G - Physics

11

C

352/82

G11C 11/34 (2006.01) G11C 8/00 (2006.01) G11C 8/08 (2006.01) G11C 8/10 (2006.01) G11C 8/18 (2006.01)

Patent

CA 1167962

22 ROW DRIVER CIRCUIT FOR SEMICONDUCTOR MEMORY ABSTRACT A circuit (10) is disclosed for use in a semiconductor integrated circuit memory. The integrated circuit memory includes row lines (102-108) which serve to activate the access transistors for memory cells (102a-108a) within the memory circuit. A row decoder circuit (36) receives a plurality of first address bits and produces a drive signal output when the decoder circuit is selected. A transition detector circuit (24) produces a transition signal whenever the state of any of the address bits is changed. A clock decoder circuit receives a plurality of second address bits together with the transition signal to produce a selected clock signal (.PHI.A-.PHI.D)- The combination of the transition signal and the output of the row decoder circuit (36) serves to precharge the gate terminals of the row driver transistors (80-86) for the row lines (102-108). The selected row line receives the active state of the clock signal (.PHI.A-.PHI.D) which causes the gate terminal of the selected row driver transistor to be capacitively coupled to a higher voltage than the clock signal to therefore supply the full clock signal voltage to the row line (102-108). The voltage on the row line then activates the access transistors (118, 120) for the memory cells (106a) on the row line (106). This enables a maximum charge to be stored in or read from the memory cell (106a).

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