Sample and hold circuit

Details Sample and hold circuit Sample and hold circuit

G - Physics

11

C

328/172

G11C 27/02 (2006.01) H03M 1/00 (2006.01)

Patent

CA 1109933

ABSTRACT OF THE DISCLOSURE A low drift sample and hold circuit is disclosed comprising a transconductance input buffer coupled at its output to a plurality of CMOS inverters through a respective plurality of CMOS switches. The appropriate switches are momentarily addressed by a micro-processor while applying a respective input value to the buffer. The buffer is de-activated prior to the opening of the switch to prevent errors between the sampled and held values.

314494

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