Sample/hold amplifier for integrated circuits

G - Physics – 11 – C

Patent

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330/8

G11C 27/02 (2006.01)

Patent

CA 1287128

935.132 ABSTRACT OF THE DISCLOSURE A sample/hold amplifier comprising two trans- conductance stages with their inverting input terminals connected together. In sample mode, the input signal is connected to the non-inverting input of the first stage, and a hold capacitor is connected to the non-inverting input terminal of the second stage and driven by the amplifier output through a feedback circuit which forces the hold capacitor voltage to track the input signal. Upon switchover to hold mode, the roles of the two trans- conductance stages are interchanged: The non-inverting input terminal of the first stage is connected through a feedback circuit to the amplifier output, and the second stage receives as an input signal the voltage of the hold capacitor, which now is disconnected from the amplifier output. The net offset voltage developed on the hold capacitor is the difference between the respective offsets of the two transconductance stages. This net offset volt- age is compensated for by an equal and opposite voltage in hold mode, due to the interchange of roles of the two transconductance stages.

589538

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