Sample timing and carrier frequency estimation circuit for...

Details Sample timing and carrier frequency estimation circuit for... Sample timing and carrier frequency estimation circuit for...

H - Electricity

04

B

H04B 1/40 (2006.01) H03D 3/00 (2006.01) H04L 7/04 (2006.01) H04L 27/233 (2006.01)

Patent

CA 2065638

RD-20, 181 SAMPLE TIMING AND CARRIER FREQUENCY ESTIMATION CIRCUIT FOR SINE-COSINE DETECTORS ABSTRACT A digital radio receiver for synchronization of radiowave transmissions for digital and analog FM signals in TDMA systems such as cellular telephones uses a Sine/Cosine detector that minimizes the bit error rate. The detector employs an A/D converter that samples a received intermediate frequency signal, a sorter circuit that produces a predetermined number of samples to be used in the decoding based upon a sample timing adjustment, and a sample and phase adjustment circuit that selects samples based on a sample timing adjustment and adds a Carrier phase adjustment to the samples. A cosine detector and a sine detector decode the sample into a cosine and a sine of the transmitted phase angle, respectively. The amplitudes of the cosine detector and sine detector output signals are measured by a cosine level check circuit and a sine level check circuit respectively. A decision logic produces a pair of bits from the levels detected by the cosine level check circuit and the sine level check circuit as the decoded transmitted information. Adjustments to the sample timing and carrier phase are performed by an adjustment circuit that monitors the phase error between the decoded information and a predetermined information set in the preamble of each TDMA slot. The adjustment circuit sends the sample timing and carrier phase adjustments to the SPA circuit which selects different samples to be decoded and uses the carrier phase adjustment to recalculate different coefficients from these samples and pass the signal through the remainder of the circuit and eventually to the adjustment circuit. The signal is iteratively cycled through this loop until the best sample timing and carrier phase adjustments are reached.

Affiliated with

Also associated with

Rating

Sample timing and carrier frequency estimation circuit for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Sample timing and carrier frequency estimation circuit for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sample timing and carrier frequency estimation circuit for... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1922284