Sampling clock correction circuit

Details Sampling clock correction circuit Sampling clock correction circuit

H - Electricity

04

L

340/74

H04L 1/00 (2006.01) H04L 7/02 (2006.01)

Patent

CA 1128160

ABSTRACT OF THE DISCLOSURE A circuit for maintaining proper sampling timing in a data modem wherein main channel equalizer error is correlated with a derivative channel signal to drive a clock correction signal. The derivative channel signal is derived from an equa- lizer using fewer coefficients than required to derive the main channel equalized signal, and calculation of the equalized derivative and clock correction signal is performed only once every other Baud.

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