Scalable inter-processor and processor to i/o messaging...

Details Scalable inter-processor and processor to i/o messaging... Scalable inter-processor and processor to i/o messaging...

G - Physics

06

F

G06F 15/00 (2006.01) G06F 15/173 (2006.01)

Patent

CA 2073174

2073174 9110197 PCTABS00006 A massively parallel computer system (500) is disclosed having a global router network in which pipeline registers are spatially distributed to increase the messaging speed of the global router network. The global router network includes an expansion tap for processor to I/O (1700) messaging so that I/O messaging bandwidth matches interprocessor messaging bandwidth. A route-opening message packet includes protocol bits which are treated homogeneously with steering bits. The route-opening packet further includes redundant address bits for imparting a multiple-crossbars personality to router chips within the global router network. A structure and method for spatially supporting the processors (700) of the massively parallel system and the global router network are also disclosed.

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