Scaleable integrated data processing device

H - Electricity – 01 – L

Patent

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Details

H01L 21/768 (2006.01) H01L 21/822 (2006.01) H01L 21/98 (2006.01) H01L 25/18 (2006.01) H01L 51/40 (2006.01)

Patent

CA 2333973

A scaleable integrated data processing device comprises a processing unit with one or more processors and a storage unit with one or more memories provided respectively in one or more processor layers (P), memory layers (M) or combined processors/memory layers (MP) which form main layers in the device. Each main layer comprises electrical conducting structures which form internal electrical connections in three dimensions in the layer. The data processing device also comprises a carrier substrate. Each main layer (P,M,MP) is formed of a number of sublayers, which each comprises respectively dielectric, semiconducting and electrical conducting portions which are provided such that they form integrated active and passive circuit elements which are included in the processors and the memories, the circuit elements, the processors and the memories being mutually connected by the electrical conducting structures in each main layer. Further electrical conducting structures are provided in the data processing device in order to interconnect the main layers mutually and/or the main layers with the substrate or in order to create a connection to the exterior of the data processing device. The integrated data processing device has a scalable architecture such that it in principle can be configured with almost unlimited processor and memory capacity. Particularly can the data processing device implement various forms of scalable parallel architectures integrated with optimal interconnectivity in three dimensions.

Dispositif de traitement de données intégré à géométrie variable, notamment micro-ordinateur, comprenant une unité de traitement constituée d'un ou de plusieurs processeurs et une unité de stockage constituée d'une ou de plusieurs mémoires. Le dispositif de traitement de données, positionné sur un substrat support (5), comprend des couches adjacentes (P, M, MP) empilées sensiblement parallèles. L'unité de traitement et l'unité de stockage sont disposées dans une ou plusieurs de ces couches. Les différentes couches sont formées d'un nombre sélectionné de processeurs et de mémoires, associés de façon à former des combinaisons sélectionnées. Chaque couche renferme des structures conductrices horizontales, qui constituent les connexions électriques internes de la couche, ainsi que d'autres structures conductrices qui constituent les connexions électriques avec les autres couches et avec l'extérieur du dispositif de traitement. Du fait de son architecture variable, ce dispositif de traitement de données intégré peut en principe être configuré avec une capacité pratiquement illimitée de processeurs et de mémoires. Il peut notamment être réalisé avec diverses formes d'architectures parallèles variables et une interconnectabilité tridimensionnelle optimale.

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