Scannable interface to non-scannable microprocessor

G - Physics – 06 – F

Patent

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G06F 11/28 (2006.01) G06F 11/267 (2006.01)

Patent

CA 2126394

A diagnostic system for diagnosing states of circuit elements is described, wherein scannable circuits can be scanned without disturbing the state of unscannable circuits of violating protocols of busses on which unscannable devices are attached. One unscannable device is a standardized microprocessor. A processor interface circuit is coupled between the microprocessor and scannable processor circuits, via a processor bus, to insulate the scannable processor circuits from the unscannable microprocessor. The processor interface circuit is also scannable, including memory elements which affect the bus, by preventing a scan when the bus is in use. A scan is prevented through the use of a maintenance request signal from a scan controller to the processor interface circuit, and one or more maintenance approval signals from the processor interface circuit to the scan controller.

Système de diagnostique permettant de diagnostiquer l'état d'éléments de circuits, les circuits analysables pouvant être analysés sans perturber l'état des circuits non analysables ni violer les protocoles de bus sur lesquels sont connectés des dispositifs non analysables. Un microprocesseur normalisé, p. ex., est un dispositif non analysable. Un circuit d'interface de processeur est monté entre le microprocesseur et les circuits processeurs analysables, au moyen d'un bus de processeur, afin de les isoler du microprocesseur non analysable. On peut aussi analyser le circuit d'interface de processeur, y compris les éléments de mémoire qui affectent le bus, en empêchant l'analyse lorsque le bus est actif. Pour empêcher une analyse, on utilise un signal de demande de maintenance transmis d'un contrôleur d'analyse au circuit d'interface de processeur, et un signal d'approbation de maintenance ou plus transmis du circuit d'interface de processeur au contrôleur d'analyse.

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