Segmented parallel rail paths for input/output signals

Details Segmented parallel rail paths for input/output signals Segmented parallel rail paths for input/output signals

H - Electricity

03

K

328/125, 356/30

H03K 19/08 (2006.01) H01L 23/535 (2006.01) H01L 27/112 (2006.01) H03K 19/177 (2006.01)

Patent

CA 1045214

ABSTRACT This specification describes an orderly arrangement of input and output lines for a programmable logic array chip (PLA). In the arrange- ment, a plurality of parallel current conducting lines called rails are positioned on the chip along side the arrays of the PLA. The inputs and outputs of the arrays are selectively connected to individual rails so that the rails carry the input signals to the arrays from off the chip and take output signals of the arrays off the chip and to inputs of the arrays. The rails are selectively segmented so that each segment of a rail may be used as a path for an input and/or output signal without interfering with signals on other segments of the same rail.

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