Selectable clocking architecture

Details Selectable clocking architecture Selectable clocking architecture

H - Electricity

03

M

H03M 9/00 (2006.01) H04L 7/02 (2006.01)

Patent

CA 2480222

A technique includes providing a first clock signal to a parallel-to-serial data conversion circuit (54) and providing a second clock signal to a memory (52) storing data for conversion by the conversion circuit. One of the first and second clock signals is selectively synchronized to a reference clock signal. The other clock is synchronized to said first or second clock. The synchronization circuit can be selectively place in a first operational mode, to synchronize the first clock to the reference clock or in a second operational mode, to synchronize the second clock to the reference clock.

A technique includes providing a first clock signal to a parallel-to-serial data conversion circuit (54) and providing a second clock signal to a memory (52) storing data for conversion by the conversion circuit. One of the first and second clock signals is selectively synchronized to a reference clock signal. The other clock is synchronized to said first or second clock. The synchronization circuit can be selectively place in a first operational mode, to synchronize the first clock to the reference clock or in a second operational mode, to synchronize the second clock to the reference clock.

Affiliated with

Also associated with

Rating

Selectable clocking architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Selectable clocking architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selectable clocking architecture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1843975