Selective calling receiver

Details Selective calling receiver Selective calling receiver

H - Electricity

04

B

H04B 1/16 (2006.01) H04L 1/00 (2006.01) H04Q 7/16 (2006.01) H04Q 7/18 (2006.01)

Patent

CA 2064315

A selective calling receiver includes a decoder having a reference clock oscillator and a CPU having a CPU operating clock oscillator. The decoder includes a timing control circuit for generating a timing signal in synchronism with a synchronizing signal contained in a POCSAG signal and a BCH error correcting circuit for extracting a message code from the POCSAG signal. If the CPU is supplied with a message code from the decoder when no timing signal is inputted from the decoder, the CPU stores the message code in RAM in the CPU or a buffer memory area of external RAM connected to the CPU. In this case, the CPU operates with a first clock signal generated by the reference clock oscillator. When the CPU is supplied with the timing signal from the decoder, the CPU reads the message code from the RAM or the buffer memory area and processes the message code with a second clock signal generated by the CPU operating clock oscil- lator and the second clock signal has a frequency higher than the frequency of the first clock signal.

Affiliated with

Also associated with

Rating

Selective calling receiver does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Selective calling receiver, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selective calling receiver will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1877788