Selective guest system purge control

Details Selective guest system purge control Selective guest system purge control

G - Physics

06

F

354/230.5

G06F 9/44 (2006.01) G06F 9/455 (2006.01) G06F 9/48 (2006.01) G06F 12/10 (2006.01)

Patent

CA 1213986

ABSTRACT OF THE DISCLOSURE The disclosed embodiments enable address translations for a virtual machine in the TLB of a CPU to be retained from exiting a SIE (start interpretive execution) instruction to the next SIE entry to interpretive execution for the same guest (virtual machine CPU). Conditions are defined which determine when guest TLB entries must be invalidated. These conditions require invalidation of guest TLB entries only within and on entry to interpretive execution. A single invalidation of guest TLB entries on entry to interpretive execution is required for any number of conditions recognized while a CPU is not in interpretive execution state. For a guest in a virtual multi-processor (MP) machine, an interlock is provided lo allow the use of guest virtual addresses by host instruction simulation and the need for guest TLB invalidation is broadcast to all other real CPUs in a real MP system so that all guest TLBs on all real CPUs can be invalidated to maintain integrity. No broadcast or interlock is needed for a guest in a virtual uni-processor (UP) machine.

465434

Affiliated with

Also associated with

Rating

Selective guest system purge control does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Selective guest system purge control, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selective guest system purge control will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1288342