Selective receiver for each processor in a multiple...

Details Selective receiver for each processor in a multiple... Selective receiver for each processor in a multiple...

G - Physics

06

F

354/230.82

G06F 15/16 (2006.01) G06F 15/17 (2006.01)

Patent

CA 1309503

Abstract of the Disclosure Circuitry, and associated methodology, in a parallel processing system (50) for sharing the address space among a plurality of autonomous processors (110,210,310) communicating over a common bus provides an efficient, non-destructive data transfer and storage environment. This is effected by augmenting each processor with buffer means (e.g. 140) for storing data received off the bus, and means (e.g. 120,130) for selectively enabling the buffer means to accept those segments of data having addresses allocated to the given processor. To avoid overwriting of data during bus conflicts, the buffer means are arranged to store data on a first-in, first-out basis and to control the processing states and data transfer in correspondence to respective bus and processor states.

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