Selectively accessible memory having an active load

Details Selectively accessible memory having an active load Selectively accessible memory having an active load

G - Physics

11

C

352/82

G11C 11/40 (2006.01) G11C 11/411 (2006.01) H01L 27/10 (2006.01) H01L 27/102 (2006.01)

Patent

CA 1259135

16 ABSTRACT The memory according to the invention is of the selectively accessible type having an active load comprising two half-cells (T1b,T3b) (T2b,T4b) each constituted by two transistors of opposite types fed back to each other. One of the transistors (T1b,T2b) of each half-cell is a multi- emitter transistor, one emitter (E1) serving to supply the hold current and the other emitter (E2) being connected to a column selection conductor (15). In order to avoid that a reverse current flows and enters into the second emitter (E2) when the cell is in the non-selected mode, a diode (D1,D2) is arranged so as to shunt the emitter/base junction of the mono-emitter transistors(T3b,T4b).

505470

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