Self-aligned channel stop

Details Self-aligned channel stop Self-aligned channel stop

H - Electricity

01

L

356/138

H01L 21/76 (2006.01) H01L 21/762 (2006.01)

Patent

CA 1258140

ABSTRACT OF THE DISCLOSURE Disclosed is a structure having two highly and similarly doped, e.g., P+ type, regions embedded in close juxtaposition in a trench-isolated N type silicon mesa which contains the novel feature of N+ channel stops embedded in the N type mesa between the P type regions. The channel stops are self-aligned to the walls of trench to arrest charge leakage between the P type regions due to parasitic transistor action along the trench wall. The P type regions may constitute two resistors, the emitter and collector of a lateral PNP transistor, etc. The dopant concentration in the channel stops is about one to two orders of magnitude higher than that in the N type silicon. Disclosed too is a process of forming channel stops which starts with a, for example, N type silicon substrate having on the surface thereof an insulator trench mask defining the region of silicon where an isolation trench is desired. A blockout mask having an opening in correspondence with the portion of the would-be silicon mesa where a channel stop is desired is formed. N type dopant is introduced into the exposed silicon followed by an anneal step to laterally diffuse the dopant into the silicon body. The exposed silicon is etched forming a deep trench which delin- eates silicon mesa having at a section of the peripher- al portion thereof a shallow and highly N doped region. Upon forming a pair of highly P doped regions on either side of the shallow highly N doped region, the latter functions as a channel stop to arrest charge leakage between the P doped regions due to parasitic FET action at the trench walls.

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