Self-aligned cmos process for bulk silicon and insulating...

Details Self-aligned cmos process for bulk silicon and insulating... Self-aligned cmos process for bulk silicon and insulating...

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H01L 21/8238 (2006.01) C30B 35/00 (2006.01) H01L 21/033 (2006.01) H01L 27/092 (2006.01) H01L 27/12 (2006.01) H01L 29/08 (2006.01) H01L 29/786 (2006.01)

Patent

CA 1057862

Application for Patent of GREGORIO SPADEA for SELF-ALIGNED CMOS PROCESS FOR BULK SILICON AND INSULATING SUBSTRATE DEVICE ABSTRACT OF THE INVENTION The method for fabrication of a self-aligned gate CMOS structure which employs no additional masking steps as compared to the standard CMOS fabrication process, this improved process providing the advantages of self-alignment between the N+ and P+ source and drain diffusions with respect to their gate regions, and metal contact openings which do not overlap the edges of the P+ or N+ source and drain regions. The self- aligning gate region is defined by a silicon nitride gate layer. Several embodiments of the novel process are described.

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